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general description the max17100 includes a high-voltage step-up regula-tor, three high-performance operational amplifiers, two linear regulators, two high-voltage switch control blocks for gate-driver supply modulation, a digital vcom cali- brator, and six independent scan drivers. the dc-dc converter is a 1.2mhz current-mode step- up regulator with a built-in power mosfet and pro- vides the regulated supply voltage for the panel source driver ics. the built-in power mosfet allows output voltages to be as high as 18v from inputs of 2.5v to 6v. a built-in 7-bit digital soft-start function limits inrush cur- rents during startup. the step-up regulator provides fast transient response to pulsed loads while producing efficiencies over 87%. three operational amplifiers, typically used as the gamma correction divider string, are configured as unity-gain buffers and feature high output short-circuit current (200ma), fast slew rate (45v/s), and wide bandwidth (20mhz). their rail-to-rail inputs and outputs maximize application flexibility. two linear regulators provide regulated gate-on and gate-off supplies for tft panel. the two high-voltage switch control blocks modulate the shape of the gate- on supply with adjustable startup delay. one operational amplifier is designed to drive the lcd backplane (vcom). it features high short-circuit current of 200ma. the programmable vcom calibrator adjusts the vcom output-voltage level through serial interface by sinking a programmable current from the vcom resistor-divider. the calibrator includes nonvolatile memory cells that store the desired vcom voltage level. the six independent high-voltage level-shifting scan drivers are designed to drive the tft panel gate lines. the outputs swing from +35v (maximum) to -15v (mini- mum) and can swiftly drive capacitive loads. the max17100 is available in a lead-free, 48-pin, thin qfn package with 0.4mm lead spacing. the package is a 6mm x 6mm square with a maximum thickness of 0.8mm for ultra-thin lcd panel design. applications lcd monitorslcd tvs features ? 2.5v to 6v input supply range ? 1.2mhz current-mode step-up converter fast transient response to pulsed loadhigh-accuracy output voltage (1%) built-in 20v, 3a, 0.16 ? n-channel power mosfetcycle-by-cycle current limit high efficiency (87%) ? three high-performance operational amplifier s 200ma output short-circuit current45v/? slew rate 20mhz, -3db bandwidth rail-to-rail inputs and outputs ? linear regulator for gate-on and gate-off supply ? two logic - controlled high-voltage switches with adjustable delay ? programmable vcom calibrator 7-bit adjustable current-sink outputserial interface nonvolatile setting memory ? six independent level - shifting scan drivers ? built-in sequencing ? soft-start and timer-delayed fault latch for allregulator outputs ? thermal-overload protection ? gate driver for external input-side series mosfet max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ________________________________________________________________ maxim integrated products 1 ordering information 19-4644; rev 1; 8/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max17100etm+ -40c to +85c 48 thin qfn-ep* pin configuration and minimal operating circuit appear at end of data sheet. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 2 _______________________________________________________________________________________ absolute maximum ratingselectrical characteristics (v in = +3v, circuit of figure 2, v main = v sup = +14v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, yv1c_, gate to agnd ...................................-0.3v to +7.5v scl, sda, wr , rst , rset, st_, ck_, ckb_ to agnd ...................................................-0.3v to +7.5v tgs, ref, comp, fb, fbn, fbp, to agnd ...................................................-0.3v to (v in + 0.3v) pgnd, ognd to agnd ........................................-0.3v to +0.3v lx to pgnd ............................................................-0.3v to +20v sup to ognd.........................................................-0.3v to +20v drvn to agnd ...................................(v in - 30v) to (v in + 0.3v) drvp to agnd.......................................................-0.3v to +40v ghon to agnd .....................................................-0.3v to +40v goff to agnd.......................................................-20v to +0.3v ghon to goff ......................................................-0.3v to +50v ghd_ to agnd......................................-0.3v to (v ghon + 0.3v) sth_, ckh_, ckbh_............(-0.3v + v goff ) to (v ghon + 0.3v) pos_, out_, comfb, comadj, vcom to ognd.....................................-0.3v to (v sup + 0.3v) comadj to comfb....................................................-6v to +6v out_ maximum continuous output current....................75ma ghon, goff rms current rating...................................130ma lx, pgnd rms current rating.............................................2.4a continuous power dissipation (t a = +70c) 48-pin tqfn (derate 27mw/c above +70c) ...........2150mw operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-65c to +160c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter conditions min tp max units in input supply range (note 1) 2.5 6 v in undervoltage lockout threshold v in rising, hysteresis = 140mv 2.05 2.25 2.45 v v fb = v fbp = 1.3v, v fbn = 0v, lx not switching 1 3 in quiescent current v fb = 1.2v, v fbp = 1.4v, v fbn = 0v, lx switching 3 5 ma duration to trigger fault condition fb or fbp below threshold or fbn above threshold; v fb = 1.14v, v fbp = 1v, v fbn = 420mv 218 ms temperature rising 160 thermal shutdown hysteresis 15 c reference ref output voltage no external load 1.238 1.250 1.262 v ref load regulation 0v < i load < 50a 10 mv ref undervoltage lockout threshold rising edge, hysteresis = 120mv 1.0 1.15 v step-up regulator output-voltage range v s 18 v frequency 1000 1200 1400 khz oscillator maximum duty cycle 90 91.5 93 % fb regulation voltage no load, t a = 0c to +85c 1.221 1.233 1.245 v fb fault trip level falling edge 1.10 1.14 1.17 v fb load regulation 0v < i load < 500ma, transient only -0.2 % fb line regulation v in = 2.5v to 6v 0.1 0.4 %/v fb input bias current v fb = 1.233v, t a = +25c 100 200 na fb transconductance i = 2.5a, fb = comp 80 190 300 s fb voltage gain fb to comp 2500 v/v lx current limit v fb = 1.2v, duty cycle = 75% 2.5 3 3.5 a downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds _______________________________________________________________________________________ 3 parameter conditions min tp max units lx on-resistance i lx = 200ma 0.12 0.25 lx bias current v lx = 19v, t a = +25c 10 20 a current-sense transresistance 0.10 0.20 0.30 v/a gate-on linear regulator controller fbp fault trip level v fbp falling 0.96 1.00 1.04 v fbp regulation voltage i drvp = 100a 1.231 1.250 1.269 v fbp line regulation error v in = 2.5v to 6v, i drvp = 100a -10 +10 mv fbp input bias current v fbp = 1.25v, t a = +25c -50 +50 na fbp effective load regulation error (transconductance) v drvp = 10v, i drvp = 50a to 1ma -1 -1.5 % drvp sink current v fbp = 1.1v, v drvp = 10v 1 5 ma drvp off-leakage current v fbp = 1.4v, v drvp = 34v, t a = +25c 0.01 10 a soft-start period 14 ms soft-start step size v ref / 128 v gate-off linear regulator controller fbn fault trip level v fbn rising 370 420 470 mv fbn regulation voltage i drvn = 100a, v ref - v fbn 0.985 1 1.015 v fbn line regulation error v in = 2.5v to 6v, i drvn = 100a -5 +5 mv fbn input bias current v fbn = 0.25v, t a = +25c -50 +50 na fbn effective load regulation error (transconductance) v drvn = -10v, i drvn = 50a to 1ma 11 25 mv drvn source current v fbn = 300mv, v drvn = -10v 1 5 ma drvn off-leakage current v fbn = 0v, v drvn = -25v, t a = +25c 0.01 10 a soft-start period 14 ms soft-start step size (v ref - v fbn ) /128 v positive gate-driver timing and control switches tgs capacitor charge current during startup, v tgs = 1v 4 5 6 a tgs turn-on threshold 1.19 1.25 1.31 v tgs discharge switch on-resistance during uvlo, v in = 2v 14 yv1c_ input low voltage 0.6 v v in < 4.5v 1.75 yv1c_ input high voltage v in > 4.5v 2.1 v yv1c_ input leakage current yv1c_ = agnd or in, t a = +25c -1 +1 a rising 100 yv1c_-to-ghon propagation delay falling 300 ns ghon input-voltage range 35 v electrical characteristics (continued)(v in = +3v, circuit of figure 2, v main = v sup = +14v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 4 _______________________________________________________________________________________ electrical characteristics (continued)(v in = +3v, circuit of figure 2, v main = v sup = +14v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter conditions min tp max units ghon input current yv1c_ is high, ck_, ckb_, st_ are low, (v ghon = 32.5v, v goff = -12.5v) 820 1550 a ghon to ghc_ switch on-resistance v tgs = 1.5v, yv1c_ = in 6 12 ghd_ to ghc_ switch on-resistance v tgs = 1.5v, yv1c_ = agnd 30 60 input series switch control gate output sink current gate = in 45 50 55 a gate done voltage threshold v in - v gate 1.5 2.2 v gate-on voltage v in = 5v 0.5 v buffer amplifiers sup supply range 6 18 v sup overvoltage fault threshold 18.1 19.0 19.9 v sup supply current all op amps are no load with v pos = v sup /2 13 16 ma input offset voltage v pos_ = v sup /2, t a = +25c -8 +4 +16 mv input bias current v pos_ = v sup /2, t a = +25c -50 +50 na input common-mode voltage range 0 v sup v output-voltage swing high i out_ = 5ma v sup - 100 mv output-voltage swing low i out_ = -5ma 100 mv slew rate 100 v/s -3db bandwidth r l = 10k , c l = 10pf, buffer configuration 20 mhz source: v pos_ = v sup - 3v, v out_ = v sup - 4v 115 200 short-circuit current sink: v pos_ = 3v, v out_ = 4v 115 200 ma power-supply rejection ratio (note 4) dc, 10v v sup 18v, v pos_ = 7v 100 db vcom operational amplifier input bias current v comfb = v comadj = v sup /2, t a = +25c -50 +50 na sup supply current buffer configuration, v comadj = v sup /2, no load 3 4 ma input offset voltage -8 +4 +16 mv output-voltage swing high i vcom = 75ma v sup - 1.5 v sup - 0.6 v output-voltage swing low i vcom = -75ma 0.4 1.5 v slew rate 100 v/s -3db bandwidth r l = 10k , c l = 10pf, buffer configuration 20 mhz buffer configuration, source: v comadj = v sup - 3v, v vcom = v sup - 4v short-circuit current buffer configuration, sink: v comadj = 3v, v vcom = 4v 115 200 ma downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds _______________________________________________________________________________________ 5 electrical characteristics (continued)(v in = +3v, circuit of figure 2, v main = v sup = +14v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter conditions min tp max units programmable vcom calibrator sup input range for memory writing 8 18 v rset voltage resolution 7 bits rset differential nonlinearity monotonic overtemperature -1 +1 ls b rset zero-scale error -1 +1 +2 lsb rset full-scale error -4 +4 lsb rset current v comadj = 4v, vcom dac code = 7fh 120 a to agnd, v sup = 18v 8.5 170 rset external resistance (note 2) to agnd, v sup = 6v 3.3 50 k v rset /v sup voltage ratio dac full scale 0.05 v/v comadj settling time to 0.5 lsb error band 20 s memory write cycles 30 cycles wr input low voltage 1 v wr input high voltage 2 v wr leakage current wr = agnd or in, t a = +25c -1 +1 a mtp write time 160 218 250 ms serial interface logic-input low voltage sda, scl 0.3 x v in v logic-input high voltage sda, scl 0.7 x v in v logic-output low sink current (sda) sda sink 3ma 0 0.4 v logic-input current sda, scl, t a = +25c -1 +1 a sda and scl input capacitance sda, scl 5 pf scl frequency (f clk ) dc 400 khz scl high time (t clh ) 600 ns scl low time (t cll ) 1300 ns sda and scl rise time (t r ) c b = total capacitance of bus line in pf 20 + 0.1 x cb 300 ns sda and scl fall time (t f ) c b = total capacitance of bus line in pf 20 + 0.1 x cb 300 ns start condition hold time (t hdstt ) 10% of sda to 90% of scl 600 ns start condition setup time (t sustt ) 600 ns data input hold time (t hddat ) 200 900 ns data input setup time (t sudat ) 100 ns stop condition setup time (t sust ) 600 ns bus free time (t bf ) 1300 ns input filter spike suppression sda, scl, not tested 50 ns downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 6 _______________________________________________________________________________________ electrical characteristics (continued)(v in = +3v, circuit of figure 2, v main = v sup = +14v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter conditions min tp max units reset function rst delay threshold voltage v ref = 1.25v 1.225 1.250 1.275 v rst sink current v rst = 0.4v 10 40 ma level shifters ghon to goff voltage range v ghon - v goff 45 v ghon input-voltage range 35 v goff input-voltage range -15 v ghon supply current yv1c_ is low, ck_, ckb_, st_ are low, (v ghon = 32.5v, v goff = -12.5v) 450 830 a yv1c_ is high, ck_, ckb_, st_ are low, (v ghon = 32.5v, v goff = -12.5v) 150 310 goff supply current yv1c_ is high, ck_, ckb_, st_ are high, (v ghon = 32.5v, v goff = -12.5v) 60 150 a st_,ck_,ckb_ input current t a = +25c -1 +1 a ckh_,ckbh_,sth_ output-voltage low i out = 10ma v goff + 0.3 v goff + 1.0 v ckh_,ckbh_,sth_ output-voltage high i out = 10ma v ghon - 1.0 v ghon - 0.3 v v in < 4.5v 1.6 st_,ck_,ckb_ input high level v in > 4.5v 2.0 v st_,ck_,ckb_ input low level 0.6 v ckh_,ckbh_,sth_ rise time (note 4) c l = 5nf, r l =50 0.5 s ckh_,ckbh_,sth_ fall time (note 4) c l = 5nf, r l =50 0.5 s ckh_,ckbh_ and sth_ propagation delay (note 4) c l = 5nf, r l =50 rising edge, falling edge 60 ns downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds _______________________________________________________________________________________ 7 electrical characteristics(v in = +3v, circuit of figure 2, v main = v sup = +14v, t a = -40 c to +85 c , unless otherwise noted.)(note 3) parameter conditions min tp max units in input supply range (note 1) 2.5 6 v in undervoltage lockout threshold v in rising, hysteresis = 140mv 2.05 2.45 v v fb = v fbp = 1.3v, v fbn = 0v, lx not switching 3 in quiescent current v fb = 1.2v, v fbp = 1.4v, v fbn = 0v, lx switching 5 ma reference ref output voltage no external load 1.238 1.262 v ref load regulation 0v < i load < 50a 10 mv ref undervoltage lockout threshold rising edge, hysteresis = 120mv 1.0 1.15 v step-up regulator output-voltage range v s 18 v frequency 1000 1400 khz oscillator maximum duty cycle 90 94 % fb regulation voltage no load 1.221 1.245 v fb line regulation v in = 2.5v to 6v 0.4 %/v fb transconductance i = 2.5a, fb = comp 75 280 s lx current limit v fb = 1.2v, duty cycle = 75% -10 +10 mv fbp effective load regulation error (transconductance) v drvp = 10v, i drvp = 50a to 1ma -1.5 % drvp sink current v fbp = 1.1v, v drvp = 10v 1 ma gate-off linear regulator controller fbn regulation voltage i drvn = 100a, v ref - v fbn 0.985 1.015 v fbn line regulation error v in = 2.5v to 6v, i drvn = 100a -5 +5 mv fbn effective load regulation error (transconductance) v drvn = -10v, i drvn = 50a to 1ma 25 mv drvn source current v fbn = 300mv, v drvn = -10v 1 ma positive gate-driver timing and control switches tgs capacitor charge current during startup, v tgs = 1v 4 6 a tgs turn-on threshold 1.19 1.31 v yv1c_ input low voltage 0.6 v v in < 4.5v 1.75 yv1c_ input high voltage v in > 4.5v 2.1 v ghon input-voltage range 35 v downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 8 _______________________________________________________________________________________ parameter conditions min tp max units yv1c_ is high, ck_, ckb_, st_ are low, (v ghon = 32.5v, v goff = -12.5v) ghon input current yv1c_ is high, ck_, ckb_, st_ are high, (v ghon = 32.5v, v goff = -12.5v) 1550 a ghon to ghc_ switch on-resistance v tgs = 1.5v, yv1c_ = in 12 ghd_ to ghc_ switch on-resistance v tgs = 1.5v, yv1c_ = agnd 60 input series switch control gate output sink current gate = in 44 55 a gate done voltage threshold v in - v gate 2.3 v gate-on voltage v in = 5v 0.61 v buffer amplifiers sup supply range 6 18 v sup overvoltage fault threshold 18.1 19.9 v sup supply current all op amps are no load with v pos = v sup /2 16 ma input offset voltage v pos_ = v sup /2, t a = +25c 16 mv input common-mode voltage range 0 v sup v output-voltage swing high i out_ = 5ma v sup - 100 mv output-voltage swing low i out_ = -5ma 100 mv source: v pos_ = v sup - 3v, v out = v sup - 4v 115 short-circuit current sink: v pos_ = 3v, v out_ = 4v 115 ma vcom operational amplifier sup supply current buffer configuration, v comadj = v sup /2, no load 4 ma output-voltage swing high i vcom = 75ma v sup - 1.5 v output-voltage swing low i vcom = 75ma 0.4 1.5 v buffer configuration, source: v comadj = v sup - 3v, v vcom = v sup - 4v short-circuit current buffer configuration, sink: v comadj = 3v, v vcom = 4v 115 ma electrical characteristics (continued)(v in = +3v, circuit of figure 2, v main = v sup = +14v, t a = -40 c to +85 c , unless otherwise noted.)(note 3) downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds _______________________________________________________________________________________ 9 parameter conditions min tp max units programmable vcom calibrator sup input range for memory writing 8 18 v rset voltage resolution 7 bits rset differential nonlinearity monotonic overtemperature -1 +1 ls b rset zero-scale error -1 +2 lsb rset full-scale error -4 +4 lsb rset current v comadj = 4v, vcom dac code = 7fh 120 a to agnd, v sup = 18v 8.5 170 rset external resistance (note 2) to agnd, v sup = 6v 3.3 50 k memory write cycles 30 cycles mtp write time 160 250 ms wr input low voltage 1 v wr input high voltage 2 v serial interface logic-input low voltage sda, scl 0.3 x v in v logic-input high voltage sda, scl 0.7 x v in v logic-output low sink current (sda) sda sink 3ma 0 0.4 v scl frequency (f clk ) dc 400 khz scl high time (t clh ) 600 ns scl low time (t cll ) 1300 ns sda and scl rise time (t r ) cb = total capacitance of bus line in pf 20 + 0.1 x cb 300 ns sda and scl fall time (t f ) cb = total capacitance of bus line in pf 20 + 0.1 x cb 300 ns start condition hold time (t hdstt ) 10% of sda to 90% of scl 600 ns start condition setup time (t sustt ) 600 ns data input hold time (t hddat ) 200 900 ns data input setup time (t sudat ) 100 ns stop condition setup time (t sust ) 600 ns bus free time (t bf ) 1300 ns input filter spike suppression sda, scl, not tested 50 ns reset function rst delay threshold voltage v ref = 1.25v 1.21 1.28 v rst sink current v rst = 0.4v 10 ma level shifters ghon to goff voltage range v ghon - v goff 45 v ghon input-voltage range 35 v goff input-voltage range -15 v electrical characteristics (continued)(v in = +3v, circuit of figure 2, v main = v sup = +14v, t a = -40 c to +85 c , unless otherwise noted.)(note 3) downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 10 ______________________________________________________________________________________ t f t cll t clh t hddat t sudat t sustp t bf t r sda scl v ih v il t hdstt parameter conditions min tp max units ghon supply current yv1c_ is low, ck_, ckb_, st_ are low, (v ghon = 32.5v, v goff = -12.5v) 830 a yv1c_ is high, ck_, ckb_, st_ are low, (v ghon = 32.5v, v goff = -12.5v) 310 goff supply current yv1c_ is high, ck_, ckb_, st_ are high, (v ghon = 32.5v, v goff = -12.5v) 150 a ckh_, ckbh_, sth_ output-voltage low i out_ = 10ma v goff + 1 v ckh_, ckbh_, sth_ output-voltage high i out_ = 10ma v ghon - 1 v v in < 4.5v 1.6 st_, ck_, ckb_ input high level v in > 4.5v 2.0 v st_, ck_, ckb_ input low level 0.6 v electrical characteristics (continued)(v in = +3v, circuit of figure 2, v main = v sup = +14v, t a = -40 c to +85 c , unless otherwise noted.)(note 3) note 1: for 5.5v < v in < 6.0v, use ic for no longer than 1% of ic lifetime. for continuous operation, input voltage should not exceed 5.5v. note 2: rset external resistor range is verified at dac full scale. note 3: specifications to t a = -40c are guaranteed by design, not production tested. note 4: guaranteed by design. not production tested. figure 1. timing definitions used in the electrical characteristics downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 11 step-up regulator efficiency vs. load current maax17100 toc01 load current (ma) efficiency (%) 100 45 50 55 60 65 70 75 80 85 9040 10 1000 v in = 3.3v v s = 5.0v v s = 3.3v step-up regulator switching frequency vs. input voltage max17100 toc02 in voltage (v) switching frequency (khz) 5.0 4.5 4.0 3.5 3.0 1210 1220 1230 1240 12501200 2.5 5.5 in supply quiescent current vs. in voltage max17100 toc03 in voltage (v) current (ma) 5.0 4.5 4.0 3.5 3.0 1 2 3 4 5 60 2.5 5.5 switching (i main = 100ma) nonswitching step-up regulator output load regulation vs. load current max17100 toc04 load current (ma) load regulation error (%) 100 10 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 -1.0 1 1000 v in = 3.3v v s = 5.0v v s = 3.3v positive linear regulator load regulation vs. load current max17100 toc05 load current (ma) load regulation error (%) 20 10 -0.6 -0.4 -0.2 0 0.2 -0.8 03 0 positive linear regulator line regulation vs. input voltage max17100 toc06 input voltage (v) line regulation error (%) 31 30 29 28 27 0 0.1 0.2 0.3 0.4 0.5 -0.1 26 32 v s = 5.0v v in = 3.3v i ghon = 20ma negative linear regulator load regulation vs. load current maax17100 toc07 load current (ma) load regulation error (%) 20 10 -0.6 -0.4 -0.2 0 0.2 -0.8 03 0 negative linear regulator line regulation vs. input voltage max17100 toc08 input voltage (v) line regulation error (%) -12 -14 -16 -18 -0.4 -0.2 0 0.2 -0.6 -20 -10 v s = 5.0v v in = 3.3v i goff = 20ma typical operating characteristics (circuit of figure 2, v s = 5v, v main = 14v, v ghon = 25v, v goff = -10v, t a = +25c, unless otherwise noted.) downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 12 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 2, v s = 5v, v main = 14v, v ghon = 25v, v goff = -10v, t a = +25c, unless otherwise noted.) step-up regulator soft-start (heavy load) max17100 toc09 2ms/div v s 5v/div0v v main 10v/div v gate 5v/div0v v lx 0v0v r l on v main = 47 ? step-up regulator pulsed load-transient response max17100 toc10 10 s/div load current1a/div v main (ac-coupled)200mv/div 0 l1 = 3.0 h r comp = 180k ? c comp = 220pf inductorcurrent 50ma2a/div 0a operational amplifier small-signal step response max17100 toc15 200ns/div v outx v posx 100mv/div(ac-coupled) 0v 100mv/div(ac-coupled) 0v step-up regulator load-transient response (50ma to 500ma) max17100 toc11 100 s/div load current500ma/div v main (ac-coupled)200mv/div 0 inductor current 50ma2a/div 0a l1 = 3.0 h r comp = 180k ? c comp = 220pf power-up sequence max17100 toc12 4ms/div v s v main v lx i l1 v ghon v goff 0v0v 0v 0v 0v 0v r l on v main = 47 ? v s : 5v/div i l1 : 1a/div v main : 10v/div v ghon : 20v/div v lx : 10v/div v goff : 20v/div operation amplifier frequency response max17100 toc13 frequency (hz) gain (db) 10k 1k -8 -6 -4 -2 0 2 -10 100 100k no load 100pf load operational amplifier large-signal step response max17100 toc14 1 s/div v outx v posx 5v/div 5v/div0v 0v v sup = 10v downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 13 operational amplifier load-transient response max17100 toc17 400ns/div i outx 100ma/div v outx ac-coupled1v/div 0v 0ma calibrator full-scale upward step response max17100 toc18 10 s/div v com 5v/div6.941v 4.221v scl5v/div 0v sda 5v/div 0v 0mv v rset 500mv/div calibrator full-scale downward step response max17100 toc19 10 s/div v com 5v/div6.941v 4.221v scl5v/div 0v sda 5v/div 0v 0mv v rset 500mv/div scan driver input/output waveforms with logic input max17100 toc20 4 s/div v st1 5v/div0v v sth1 10v/div c l = 100pf 0v sth1 rising edge propagation delay max17100 toc21 20ns/div v st1 5v/div0v v sth1 10v/div c l = 100pf 0v ck1 falling edge propagation delay max17100 toc22 20ns/div v st1 5v/div0v v sth1 10v/div c l = 100pf 0v scan driver output rise time max17100 toc23 400ns/div v st1 5v/div0v v sth1 10v/div c l = 4.7nf 0v scan driver output fall time max17100 toc24 200ns/div v st1 5v/div0v v sth1 10v/div c l = 4.7nf 0v typical operating characteristics (continued) (circuit of figure 2, v s = 5v, v main = 14v, v ghon = 25v, v goff = -10v, t a = +25c, unless otherwise noted.) operational amplifier rail-to-rail input/output max17100 toc16 4 s/div v outx 5v/div0v v posx 5v/div0v v sup = 10v downloaded from: http:///
pin description pin name function 1 comp step-up regulator error-amplifier compensation pin. connect a series rc from comp to agnd. 2 drvn gate-off linear-regulator base-drive output. open drain of an internal n-channel mosfet. connect drvn to the base of an external npn pass transistor. 3 fbn gate-off linear regulator feedback input. fbn regulates to 250mv (n ominal). connect fbn to the center of a resistive voltage-divider between the negative output and ref to se t the gate-off linear-regulator output voltage. place the resistive voltage-divider within 5mm of fbn. 4 ref reference output. bypass ref to agnd with a minimum 0.22f capacitor clo se to the pin. all power outputs are disabled until ref exceeds its uvlo threshold. 5, 42 agnd analog ground. connect to power ground (pgnd) under the ic. 6 fbp gate-on linear-regulator feedback input. fbp regulates to 1.25v (nomi nal). connect fbp to the center of a resistive voltage-divider between the positive charge-pump regulator output and agnd to set the gate-on linear-regulator output voltage. place the resistive voltage-divide r within 5mm of fbp. 7 drvp gate-on linear-regulator base-drive output. open drain of an internal n-channel mosfet. connect drvp to the base of an external pnp pass transistor. 8 tgs high-voltage-switch delay input. connect a capacitor from tgs to agn d to set the high-voltage-switch startup delay. 9 ghon high-voltage-switch input. source of the internal high-volta ge p-channel mosfet. bypass ghon to pgnd with a minimum of 0.1f capacitor close to the pin. 10, 11 ghd_ high-voltage-switch input. drain of the internal hi gh-voltage back-to-back p-channel mosfets. 12 goff gate-off voltage input for level shifter 13 ckbh2 level-shifter output 14 ckh2 level-shifter output 15 sth2 level-shifter output 16 ckbh1 level-shifter output 17 ckh1 level-shifter output 18 sth1 level-shifter output 19, 26 yv1c_ high-voltage-switch control input. when yv1c_ is high, the high-volt age switch between ghon and ghc_ is on and the high-voltage switch between ghc_ and ghd_ is off. wh en yv1c_ is low, the switch between ghon and ghc_ is off and the switch between ghc_ and ghd_ is on. yv1c _ is inhibited by the in undervoltage lockout and when the voltage on tgs is less than 1.25 v. 20 ckb2 level-shifter logic-level input 21 ck2 level-shifter logic-level input 22 ckb1 level-shifter logic-level input 23 ck1 level-shifter logic-level input 24 st2 level-shifter logic-level input 25 st1 level-shifter logic-level input max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 14 ______________________________________________________________________________________ downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 15 pin description (continued) pin name function 27, 29, 31 pos_ operational amplifier noninverting input 28, 30, 32 out_ operational amplifier output. out_ is high impedance in shutdown. 33 vcom vcom buffer operational amplifier output 34 comfb vcom buffer operational amplifier inverting input 35 sup operational amplifier supply input. typically connected to the output of the step-up regulator (v main ) and bypass to ognd with a 0.47f capacitor. 36 ognd analog ground for operati onal amplifiers. connect to power gr ound (pgnd) underneath the ic. 37 comadj vcom buffer operational amplifier noninverting inpu t 38 rset full-scale sink-current adjustment input. connect a resistor, r rset , from rset to agnd to set the full- scale adjustable sink current i out , which is v sup /(20 x r rset ). i out is equal to the current through r rset . 39 wr serial write-protect input. when wr is high, i 2 c write commands to update nonvolatile memory are ignored. 40 scl seria interface clock input. connect a 5.6k pullup resistor to in. 41 sda seria interface data i/o. output is open drain. connect a 5.6k pullup resistor to in. 43 in in supplies the internal reference and other internal circuitry. connect in to the i nput supply voltage and bypass in to agnd with a minimum 1f ceramic capacitor. it is i mportant for the loop area between the ic and the bypass capacitor, and the trace length connecting the bypass ca pacitor to be minimized. 44 gate external p-channel mosfet gate drive. it is high to keep the sw itch off during fault condition, including output overload, short circuit, fb fault latch, and thermal prot ection. leave the pin unconnected if the external pfet is not placed. 45 lx step-up regulator switching node. connect inductor and boost diode h ere and minimize trace area for lowest emi. 46 pgnd power ground 47 rst reset function output 48 fb step-up regulator feedback input. fb regulates to 1.233v. connect f b to the center of a resistive voltage- divider between the step-up regulator output and agnd to set the regulator s output voltage. place the resistive voltage-divider within 5mm of fb. ep exposed pad. connect ep to agnd. downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 16 ______________________________________________________________________________________ 5.6k ? 100k ? 0.1 f 0.1 f v cn v cp gate incomp 1 f v s 4.5v to 5.5v d4 q3 q1 v in v ghon c2 10 f 6.3v c1 10 f 6.3v max17100 180k ? ldo 3.3v l1 3 h 220pf ghd1 yv1c1 1k ? ghd2 1k ? 0.33 f ghon 0.33 f v in v cp v ghon 25v/20ma serial bus tgs scl yv1c2 sda wr drvp 5.6k ? 6.8k ? 0.1 f 0.47 f 0.1 f 0.47 f r4191k ? r510k ? v goff system fbpgoff st1 st2 ck1 ckb1 ck2 ckb2 sth1 sth2 ckh1 ckbh1 ckh2 ckbh2 ep 0.1 f panel v in lx fb pgnd agnd sup d1 d2 d3 c310 f 25v c410 f 25v v main 14v/500ma v main r1137k ? 1% r213.3k ? 1% 0.47 f ognd 100k ? 100k ? 100k ? 100k ? to vcom backplane 100k ? 100k ? 200k ? 200k ? pos1 pos2 pos3 comadj out1 out2 comfb vcom out3 24.9k ? rset drvn fbn r7324k ? r831.6k ? q2 v cn v goff -10v/20ma 6.8k ? ref 0.22 f 27k ? 1 f rst figure 2. typical operating circuit typical operating circuit the max17100 typical operating circuit (figure 2) is acomplete power-supply system for tft lcds. the circuit generates a +14v source-driver supply and +25v and -10v gate-driver supplies. the input-voltage range for theic is from +2.5v to +6.0v. the listed load currents in figure 2 are available from a +4.5v to +5.5v supply. table 1 lists some recommended components and table 2 lists the contact information of component suppliers. downloaded from: http:///
detailed description the max17100 contains a high-performance step-upregulator, three high-current operational amplifiers, two linear regulators, two high-voltage-switch control blocks for gate-driver supply modulation, a digital vcom cali- brator, and six independent level-shifting scan drivers. figure 3 shows the max17100 functional diagram. step-up regulator the main step-up regulator employs a current-mode,fixed-frequency pwm architecture to maximize loop bandwidth and provide fast transient response to pulsed loads typical of tft-lcd panel source drivers. the 1.2mhz switching frequency allows the use of low- profile inductors and ceramic capacitors to minimize the thickness of lcd panel designs. the integratedhigh-efficiency mosfet and the ics built-in digital soft- start functions reduce the number of external compo- nents required while controlling inrush currents. the output voltage can be set from v in to 18v with an exter- nal resistive voltage-divider. the regulator controls theoutput voltage and the power delivered to the output by modulating the duty cycle (d) of the internal power mosfet in each switching cycle. the duty cycle of the mosfet is approximated by: d v- v v main in main max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 17 table 1. component list reference designator description c1, c2 10f, 6.3v x5r ceramic capacitors (0603), tdk c1608x5r0j106k c3, c4 10f, 25v x5r ceramic capacitors (1206), tdk c3216x5r1e106m d1 3a, 30v schottky diode (m-flat), toshiba cms02 d2, d3 200ma, 100v dual diodes (sot23), fairchild mmbd4148se d4 3a, 30v diode (sma), vishay b350a l1 3.0h, 3a inductor, sumida cdrh6d28-3r0 q1 200ma, 40v pnp transistor (sot23), fairchild mmbt3906 q2 200ma, 40v npn transistor (sot23), fairchild mmbt3904 q3 -20v/63m p-channel mosfet, vishay powerpak sc-70 sia443dj table 2. component suppliers supplier phone fax website fairchild 408-822-2000 408-822-2102 www.fairchildsemi.com sumida 847-545-6700 847-545-6720 www.sumida.com tdk 847-803-6100 847-390-4405 www.component.tdk.com toshiba 949-455-2000 949-859-3963 www.toshiba.com/taec vishay 402-563-6866 402-563-6296 www.vishay.com downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 18 ______________________________________________________________________________________ serial interface v cn v cp gate step-up controller in comp switch control 1 v in max17100 ghc1 ghd1 ghd2 ghon v cp v ghon tgs scl 7 7 yv1c1 yv1c2 ghc2 sda mtp dac wrdrvp fbp st1 ghon ghc1 ghc2 st2 ck1 ckb1 ck2 ckb2 goff sth1 sth2 ckh1 ckbh1 ckh2 ckbh2 lx fb pgnd agnd sup out1 v main pos1 rset drvn fbn v cn v goff ref rst gate-on controller gate-off controller thermal shutdown switch control 2 ref voltage detector out2 pos2 out3 pos3 comfb ognd vcom comadj ep figure 3. functional diagram downloaded from: http:///
figure 4 shows the functional diagram of the step-upregulator. an error amplifier compares the signal at fb to 1.233v and changes the comp output. the voltage at comp sets the peak inductor current. as the load varies, the error amplifier sources or sinks current to the comp output accordingly to produce the inductor peak current necessary to service the load. to maintain sta- bility at high duty cycles, a slope-compensation signal is summed with the current-sense signal. on the rising edge of the internal clock, the controller sets a flip-flop, turning on the n-channel mosfet and applying the input voltage across the inductor. the current through the inductor ramps up linearly, storing energy in its magnetic field. once the sum of the current-feedbacksignal and the slope compensation exceeds the comp voltage, the controller resets the flip-flop and turns off the mosfet. since the inductor current is continuous, a transverse potential develops across the inductor that turns on the boost diode (d1). the voltage across the inductor then becomes the difference between the out- put voltage and the input voltage. this discharge con- dition forces the current through the inductor to ramp back down, transferring the energy stored in the mag- netic field to the output capacitor and the load. the mosfet remains off for the rest of the clock cycle. max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 19 soft- start 1.2mhz oscillator to fault logic 1.233v fb lx ilim comparator v limit current sense pgnd 1.14v comp clock error amp pwm comparator slope comp fault comparator logic and driver figure 4. step-up regulator functional diagram downloaded from: http:///
max17100 gate-on linear-regulator controller (reg_p) the gate-on linear-regulator controller is an analog gainblock with an open-drain n-channel output. it drives an external pnp pass transistor with a 6.8k ? base-to-emit- ter resistor (figure 2). its guaranteed base drive sinkcurrent is at least 1ma. the regulator including q1 in figure 2 uses a 0.47f ceramic output capacitor and is designed to deliver 20ma at 25v. other output voltages and currents are possible with the proper pass transis- tor and output capacitor. see the pass-transistor selection and stability requirements sections. reg p is typically used to provide the tft-lcd gate driversgate-on voltage. use a charge pump with as many stages as necessary to obtain a voltage exceeding the required gate-on voltage (see the selecting the number of charge-pump stages section). note the voltage rat- ing of drvp is 36v. if the charge-pump output voltagecan exceed 36v, an external cascode npn transistor should be added as shown in figure 5. alternately, the linear regulator can control an intermediate charge- pump stage while regulating the final charge-pump out- put (figure 6). reg p is enabled after the gate voltage reaches the gate-on threshold voltage (1.5v typ). each time it is enabled, the controller goes through a soft- start routine that ramps up its internal reference dac in 128 steps. gate-off linear-regulator controller (reg n) the gate-off linear-regulator controller (reg n) is ananalog gain block with an open-drain p-channel output. it drives an external npn pass transistor with a 6.8k ? base-to-emitter resistor (figure 2). its guaranteed base-drive source current is at least 1ma. the regulator including q2 in figure 2 uses a 0.47f ceramic output capacitor and is designed to deliver 20ma at -10v. other output voltages and currents are possible with the proper pass transistor and output capacitor (see the pass-transistor selection and stability requirements sections). reg n is typically used to provide the tft-lcd gate drivers gate-off voltage. a negative volt- age can be produced using a charge-pump circuit as shown in figure 2. reg n is enabled after the gate voltage reaches the gate-on threshold voltage (1.5v typ). each time it is enabled, the control goes through a soft-start routine that ramps down its internal reference dac from v ref to 250mv in 128 steps. operational amplifiers the max17100 has three operational amplifiers. theoperational amplifiers are typically used as the gamma- correction divider string. they feature 45v/s slew rate, and 20mhz 3db bandwidth. the rail-to-rail input and output capability maximizes application flexibility. internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 20 ______________________________________________________________________________________ max17100 drvp fbp v main from charge-pump output npn cascode transistor pnp passtransistor v ghon figure 5. using cascaded npn for charge-pump output voltages > 36v gate figure 6. linear regulator controls the intermediate charge- pump stage downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 21 short-circuit current limit the operational amplifiers limit short-circuit current toapproximately 200ma if the output is directly shorted to sup or to ognd. if the short-circuit condition persists, the junction temperature of the ic rises until it reaches the thermal-shutdown threshold (+160c typ). once the junc- tion temperature reaches the thermal-shutdown threshold, an internal thermal sensor immediately sets the thermal fault latch, shutting off all the ics outputs. the device remains inactive until the input voltage is cycled. undervoltage lockout (uvlo) the uvlo circuit compares the input voltage at in withthe uvlo threshold (2.25v typ) to ensure the input volt- age is high enough for reliable operation. the wider 140mv (typ) hysteresis prevents supply transients fromcausing a restart. once the input voltage exceeds the uvlo rising threshold, startup procedure begins. when the input voltage falls below the uvlo falling threshold, the controller turns off the main step-up regulator and the linear regulators, pulls gate high to turn off the external series p-channel mosfet and disables the switch control block. the operational-amplifier outputs become high impedance at this time. reference voltage (ref) the reference output is nominally 1.25v and can sourceat least 50a. bypass ref with a 0.22f ceramic capacitor connected between ref and agnd. gate v ref v ghc_ depends on yv1c_ input voltage ok soft-start begins soft-start ends v in v main v ref v ghon v goff v ghc_ v tgs v ghc_ is unconnected 14ms figure 7. power-up sequence downloaded from: http:///
max17100 power-up sequence and soft-start once in exceeds approximately 2.25v, the referenceturns on. and then gate is pulled high. when the refer- ence voltage exceeds 1.0v (typ), gate is pulled low to turn on the external p-channel mosfet if no output fault is detected. then the ic enables the main step-up regulator, the gate-on linear-regulator controller, and the gate-off linear-regulator controller simultaneously. the ic employs soft-start for each regulator to minimize inrush current and voltage overshoot and to ensure a well-defined startup behavior. each output uses a 7-bit soft-start dac. for the step-up and the gate-on linear regulator, the dac output is stepped in 128 steps from zero up to the reference voltage. for the gate-off linear regulator, the dac output steps from the reference down to 250mv in 128 steps. the soft-start duration is 14ms (typ) for all three regulators. a capacitor (ctgs) from tgs to agnd determines two switch-control blocks startup delay. after the soft-start routine for each regulator is complete without any fault, a 5a current source starts charging ctgs. once the capacitor voltage exceeds 1.25v (typ), both the switch- control blocks are enabled as shown in figure 7. after the switch-control blocks are enabled, ghc_ can be con- nected to ghon or ghd_ through the internal p-channel switches, depending upon the state of yv1c_. before startup and when in is less than uvlo, tgs is internally connected to agnd to discharge ctgs. select ctgs to set the delay time using the following equation: switch-control block the switch-control inputs (yv1c1 and yv1c2) are notactivated until all four of the following conditions are satisfied: the input voltage exceeds uvlo, the soft-start routine of all the regulators is complete, a no fault con- dition is detected, and vtgs exceeds its turn-on threshold. once activated and if yv1c_ is high, the 6 ? (typ) internal p-channel switch between ghon andghc_ turns on and the 30 ? (typ) p-channel switch between ghd_ and ghc_ turns off. if yv1c_ is low, the6 ? (typ) internal p-channel switch between ghon and ghc_ turns off and the 30 ? (typ) p-channel switch between ghd_ and ghc_ turns on. reset function the max17100 provides a rst signal to the system for reset purpose and at the same time the signal is usedinternally to control the timing when ic starts to down- load data from nonvolatile setting memory to the vcom calibrator. below is the sequence description for reset function: a) when v in is less than 1.0v, rst is of undefined state. b) rst will be pulled low once v in exceeds 1.0v. c) once v in exceeds v uvlo , v ref will start up. when v ref is higher than 1.0v, rst will be released and its output becomes high impedance. external rc(figure 8) will be charged up by their pullup voltage. d) when rst reaches the threshold voltage (1.25v) dur- ing charging up, the serial controller will start to down-load data from the nonvolatile memory to the vcom calibrators internal register. at this time, the system devices like timing controller will also be reset. the sequence is shown in figure 9. cd e l a y t i m e a v tgs = _ . 5 125 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 22 ______________________________________________________________________________________ internal reset ic inside rst refrdy figure 8. reset functional diagram 1.0v v in v ref v refrdy rst undefined internal reset 2.25v 1.0v 1.25v figure 9. reset function sequence downloaded from: http:///
xao function once v in drops below in uvlo, the high-side p-chan- nel mosfets of the two high-voltage switch-controlblocks will be forced to turn on regardless of yv1c_ and tgs. in the meantime, sth_ and ckh will be pulled high and ckbh_ will be of high-impedance state. fault protection during steady-state operation, if the output of the mainregulator or any of the linear-regulator outputs does not exceed its respective fault-detection threshold, the max17100 activates an internal fault timer. if any condi- tion or combination of conditions indicates a continuous fault for the fault-timer duration (218ms typ), the max17100 sets the fault latch to shut down all the out- puts and turn off the external p-channel mosfet (gate is pulled high) except the reference. once the fault condition is removed, cycle the input voltage (below the uvlo falling threshold) to clear the fault latch and reactivate the device. the max17100 also provides overvoltage protection for the output of the step-up converter by monitoring the sup pin. during normal operation, if sup is higher than the threshold voltage (19v typ), the step-up converter will stop switching and prevent excessive voltage from damaging the max17100. once sup drops below the threshold voltage, the step-up converter will restart and regulate the needed output voltage. thermal-overload protection thermal-overload protection prevents excessive powerdissipation from overheating the max17100. when the junction temperature exceeds t j = +160c (typ), a thermal sensor immediately activates the fault protec-tion, which shuts down all outputs and turns off the external p-channel mosfet (gate is pulled high) except the reference, allowing the device to cool down. cycling the input voltage (below the uvlo falling threshold) to clear the fault latch and reactivate the device. the thermal-overload protection protects the controller in the event of fault conditions. for continuous operation, do not exceed the absolute maximum junc- tion temperature rating of t j = +150c. high-voltage level-shifting scan driver the max17100 includes six independent high-voltagelevel-shifting scan drivers to drive the gate lines of the tft panel. the driver outputs (sth1, sth2, ckh1, ckbh1, ckh2, and ckbh2) swing between theirpower-supply rails (v ghon and v goff ) according to the input logic levels on the blocks inputs (st1, st2, ck1,ckb1, ck2, and ckb2). the driver output is at v goff when its respective input is logic-low, and at v ghon when its respective input is logic-high. these output sig-nals have a maximum range of +35v and -15v. vcom calibrator the vcom calibrator is a solid-state alternative tomechanical potentiometers used for adjusting the lcd backplane voltage (vcom) in tft lcd displays. the noninverting input of vcom, comadj, is internally con- nected to a programmable sink current source, which sets the vcom level (figure 10). an internal 7-bit dac controls the sink current and allows the user to increase or decrease the vcom level by a 2-wire serial interface. the dac is ratiometrically relative to the sup voltage and is monotonic over all operating conditions. the user stores the dac setting in the internal nonvolatile memory block. on power-up, the mtp presets the dac to the last stored setting. the 2-wire serial interface between the system controller and the programming circuit adjusts the dac and programs the mtp when wr is low. the resistive voltage-divider and the sup supply set the maximum value of vcom. the sink cur-rent from the voltage-divider reduces the comadj volt- age level and vcom output. the external resistor at r rset sets the full-scale sink current and the minimum value of vcom. driving pure capacitive load in general, the lcd backplane (vcom) consists of adistributed series capacitance and resistance, a load that can be easily driven by the operational amplifier. however, if the operational amplifier is used in an appli- cation with a pure capacitive load, steps must be taken to ensure stable operation. as the operational amplifiers capacitive load increases, the amplifiers bandwidth decreases and gain peaking increases. a 5 ? to 50 ? small resistor placed between out_ and the capacitive load reduces peaking but alsoreduces the gain. an alternative method of reducing peaking is to place a series rc network (snubber) in parallel with the capacitive load. the rc network does not continuously load the output or reduce the gain. typical values of the resistor are between 100 ? and 200 ? , and the typical value of the capacitor is 10nf. max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 23 downloaded from: http:///
max17100 design procedures step-up regulator inductor selection the minimum inductance value, peak current rating,and series resistance are factors to consider when selecting the inductor. these factors influence the con- verters efficiency, maximum output load capability, transient-response time, and output voltage ripple. size and cost are also important factors to consider. the maximum output current, input voltage, output volt- age, and switching frequency determine the inductor value. very high inductance values minimize the current ripple and therefore reduce the peak current, which decreases core losses in the inductor and conduction losses in the entire power path. however, large inductor values also require more energy storage and more turns of wire, which increase size and can increase conduction losses in the inductor. low inductance val- ues decrease the size but increase the current ripple and peak current. finding the best inductor involves choosing the best compromise between circuit efficien- cy, inductor size, and cost. the equations used here include a constant lir, which is the ratio of the inductor peak-to-peak ripple current to the average dc inductor current at the full load current. the best trade-off between inductor size and circuit efficiency for step-up regulators generally has an lirbetween 0.3 and 0.6. however, depending on the ac characteristics of the inductor core material and ratio of inductor resistance to other power-path resistances, the best lir can shift up or down. if the inductor resistance is relatively high, more ripple can be accepted to reduce the number of turns required and increase the wire diameter. if the inductor resistance is relatively low, increasing inductance to lower the peak current can decrease losses throughout the power path. if extreme- ly thin high-resistance inductors are used, as is com- mon for lcd-panel applications, the best lir can increase to between 0.5 and 1.0. once a physical inductor is chosen, higher and lower values of the inductor should be evaluated for efficien- cy improvements in typical operating regions. calculate the approximate inductor value using the typ- ical input voltage (v in ), the maximum output current (i main(max) ), the expected efficiency ( typ ) taken from an appropriate curve in the typical operating characteristics section, and an estimate of lir based on the above discussion: l=( v v )( v- v if )( in main main in main(max) osc t y yp lir ) internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 24 ______________________________________________________________________________________ sda sclwr v in sup r rset rset r b r a vcom v main mtp block dac 19r r 7 7 v in comadj comfb vcom serial bus serial control interface max17100 figure 10. vcom calibrator functional diagram downloaded from: http:///
choose an available inductor value from an appropriateinductor family. calculate the maximum dc input cur- rent at the minimum input voltage (v in(min) ) using con- servation of energy and the expected efficiency at thatoperating point ( min ) taken from the appropriate curve in the typical operating characteristics : calculate the ripple current at that operating point andthe peak current required for the inductor: the inductors saturation current rating and the max17100s lx current limit (i lim ) should exceed i peak , and the inductors dc current rating should exceed i in(dc,max) . for good efficiency, choose an inductor with less than 0.1 ? series resistance. considering the typical operating circuit, the maximumload current (i main(max) ) is 500ma with a 14v output and a typical input voltage of 5v. choosing an lir of 0.55 andestimating efficiency of 85% at this operating point: using the circuits minimum input voltage (4.5v) and estimating efficiency of 80% at that operating point: the ripple current and the peak current are: output-capacitor selection the total output voltage ripple has two components: thecapacitive ripple caused by the charging and discharg- ing of the output capacitance, and the ohmic ripple due to the capacitors equivalent series resistance (esr): where i peak is the peak inductor current (see the inductor selection section). for ceramic capacitors, the output voltage ripple is typically dominated by v ripple(c) . the voltage rating and temperature charac- teristics of the output capacitor must also be considered. input-capacitor selection the input capacitor (c in ) reduces the current peaks drawn from the input supply and reduces noise injec-tion into the ic. two 10f ceramic capacitors are used in the typical applications circuit (figure 2) because of the high source impedance seen in typical lab setups. actual applications usually have much lower source impedance since the step-up regulator often runs directly from the output of another regulated supply. typically, c in can be reduced below the values used in the typical applications circuit. ensure a low-noise sup-ply at in by using adequate c in . rectifier diode the max17100s high switching frequency demands ahigh-speed rectifier. schottky diodes are recommend- ed for most applications because of their fast recovery time and low forward voltage. in general, a 3a schottky diode complements the internal mosfet well. output-voltage selection the output voltage of the main step-up regulator can beadjusted by connecting a resistive voltage-divider from the output (v main ) to agnd with the center tap con- nected to fb (see figure 2). select r2 in the 10k ? to 50k ? range. calculate r1 with the following equation: where v fb , the step-up regulators feedback set point, is 1.233v. place r1 and r2 close to the ic. r1 = r2 ( v v -1) main fb v= v + v ripple ripple(c ) r ripple(esr) ripple(c v )) main out main in main osc i c v- v vf and () vi r ripple(esr esr(co ) peak u ut) i= v (14v - 4.5v) hv m h z ripple 45 30 14 12 . .. == + 0 848 2 236 . . a i = 1.94a 0.848a a peak i= 0.5a v 4.5v a in(dc,max) = 14 08 194 . . l=( 5v 14v ) vv am h z 0.85 0.55 2 ( .. )( ) 14 5 05 12 3 . .0 h i= v( v- v lv ripple in(min) main in(min) main f i= i + i 2 osc peak in(dc,max) ripple i= iv v in(dc,max) main(max) main in(min) min max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 25 downloaded from: http:///
max17100 loop compensation choose r comp to set the high-frequency integrator gain for fast transient response. choose c comp to set the integrator zero to maintain loop stability. for low-esr out-put capacitors, use the following equations to obtain sta- ble performance and good transient response: to further optimize transient response, vary r comp in 20% steps and c comp in 50% steps while observing transient-response waveforms. setting the vcom adjustment range see figure 10 for the vcom calibrator functional dia-gram. the external resistive voltage-divider sets the maximum value of the vcom adjustment range. r rset sets the full-scale sink current, i out , which determines the minimum value of the vcom adjustment range.large r rset values increase resolution, but decrease the vcom adjustment range. calculate r a , r b , and r rset using the following procedure: 1) choose the maximum vcom level (v max ), the minimum vcom level (v min ), and the v main supply voltage. 2) select r a between 10k ? and 500k ? based on the acceptable power loss from the v main supply rail connected to sup. 3) calculate r b : 4) calculate r rset : 5) verify that i rset does not exceed 120a: 6) if i rset exceeds 120a, return to step 2 and choose a larger value for r a . 7) the resulting resolution is: a complete design example follows: v max = 4v, v min = 2.4v, v sup = 8v if r a = 200k ? , then r b = 200k ? , and r rset = 24.9k ? . resolution = 12.5mv. charge pumps selecting the number of charge-pump stages for highest efficiency, always choose the lowest numberof charge-pump stages that meet the output require- ment. figures 11 and 12 show the positive and negative charge-pump output voltages for a given v main for one-, two-, and three-stage charge pumps. the number ofpositive charge-pump stages is given by: n= v+ v - v v- 2v pos ghon dropout main main d (v - v ) 127 max min i= v 20 r rset sup rset r= v 20 (v - v r rset max max min a ) r= v v- v r b max sup max a r vv c li c i comp in out out main(max) comp o 253 u ut) out main(max) comp c 10 i r internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 26 ______________________________________________________________________________________ figure 11. positive charge-pump output voltage vs. v main positive charge-pump output voltage vs. v main v main (v) v ghon (v) 18 16 14 12 20 30 6050 40 70 8010 10 20 3-stage charge pump 2-stage charge pump 1-stage charge pump v d = 0.5v figure 12. negative charge-pump output voltage vs. v main negative charge-pump output voltage vs. v main v main (v) v ghoff (v) 18 16 14 12 -50 -40 -30 -20 -10 0 -60 10 20 1-stage charge pump 2-stage charge pump 3-stage charge pump v n = 0.5v downloaded from: http:///
where n pos is the number of positive charge-pump stages, v ghon is the gate-on linear-regulator (reg p) output, v main is the main step-up regulator output, v d is the forward-voltage drop of the charge-pump diode,and v dropout is the dropout margin for the linear reg- ulator. use v dropout = 0.3v. the number of negative charge-pump stages is given by:where n neg is the number of negative charge-pump stages, v goff is the gate-off linear-regulator reg n output, v main is the main step-up regulator output, v d is the forward-voltage drop of the charge-pump diode,and v dropout is the dropout margin for the linear reg- ulator. use v dropout = 0.3v. the above equations are derived based on theassumption that the first stage of the positive charge pump is connected to v main and the first stage of the negative charge pump is connected to ground.sometimes fractional stages are more desirable for bet- ter efficiency. this can be done by connecting the first stage to v in or another available supply. if the first charge-pump stage is powered from v in , then the above equations become: flying capacitors increasing the flying capacitor (c x ) value lowers the effective source impedance and increases the outputcurrent capability. increasing the capacitance indefi- nitely has a negligible effect on output-current capabili- ty because the internal switch resistance and the diode impedance place a lower limit on the source imped- ance. a 0.1f ceramic capacitor works well in most low-current applications. the flying capacitors voltage rating must exceed the following: v cx > n x v main where n is the stage number in which the flying capaci-tor appears and v main is the output voltage of the main step-up regulator. charge-pump output capacitor increasing the output capacitance or decreasing theesr reduces the output ripple voltage and the peak-to- peak transient voltage. with ceramic capacitors, the output voltage ripple is dominated by the capacitance value. use the following equation to approximate the required capacitor value: where c out_cp is the output capacitor of the charge pump, i load_cp is the load current of the charge pump, and v ripple_cp is the peak-to-peak value of the output ripple. charge-pump rectifier diodes use low-cost silicon switching diodes with a current rat-ing equal to or greater than two times the average charge-pump input current. if it helps avoid an extra stage, some or all of the diodes can be replaced with schottky diodes with an equivalent current rating. linear-regulator controllers output-voltage selection adjust the gate-on linear-regulator (reg p) output volt-age by connecting a resistive voltage-divider from the reg p output to agnd with the center tap connected to fbp (figure 2). select the lower resistor of the divider r5 in the range of 10k ? to 30k ? . calculate the upper resistor, r4, with the following equation:where v fbp = 1.25v (typ). adjust the gate-off linear-regulator reg n output volt-age by connecting a resistive voltage-divider from v goff to ref with the center tap connected to fbn (figure 2). select r8 in the 20k ? to 50k ? range. calculate r7 with the following equation:where v fbn = 250mv, v ref = 1.25v. note that ref can only source up to 50a; avoid using a resistor less than20k ? for r8 that results in higher bias current than ref can supply. r7 = r8 v- v v-v fbn goff ref fbn r4 = r5 ( v v -1) ghon fbp c i 2f v out_cp load_cp osc ripple_cp n= v+ v + v v- 2v n= - pos ghon dropout in main d neg v v+ v + v v- 2v goff dropout in main d n= -v + v v- 2v neg goff dropout main d max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 27 downloaded from: http:///
max17100 pass-transistor selection the pass transistor must meet specifications for currentgain (h fe(min) ), input capacitance, collector-emitter saturation voltage, and power dissipation. the transis-tors current gain limits the guaranteed maximum output current to: where i drv is the minimum guaranteed base-drive cur- rent, v be is the transistors base-to-emitter forward volt- age drop, and r be is the pullup resistor connected between the transistors base and emitter. furthermore,the transistors current gain increases the linear regula- tors dc loop gain (see the stability requirements sec- tion), so excessive gain destabilizes the output.therefore, transistors with current gain over 100 at the maximum output current can be difficult to stabilize and are not recommended unless the high gain is needed to meet the load-current requirements. the transistors saturation voltage at the maximum out- put current determines the minimum input-to-output voltage differential that the linear regulator can support. also, the packages power dissipation limits the usable maximum input-to-output voltage differential. the maxi- mum power-dissipation capability of the transistors package and mounting must exceed the actual power dissipated in the device. the power dissipated equals the maximum load current (i load(max)_lr ) multiplied by the maximum input-to-output voltage differential:where v in(max)_lr is the maximum input voltage of the linear regulator and v out_lr is the output voltage of the linear regulator. stability requirements the max17100 linear-regulator controllers use an inter-nal transconductance amplifier to drive an external pass transistor. the transconductance amplifier, the pass transistor, the base-emitter resistor, and the out- put capacitor determine the loop stability. the following applies to both linear-regulator controllers in the max17100. the transconductance amplifier regulates the output voltage by controlling the pass transistors base cur- rent. the total dc loop gain is approximately: where v t is 26mv at room temperature and i bias is the current through the base-to-emitter resistor (r be ). for the max17100, the bias currents for both the gate-onand gate-off linear-regulator controllers are 0.1ma. therefore, the base-to-emitter resistor for both linear regulators should be chosen to set 0.1ma bias current: the output capacitor and the load resistance create the dominant pole in the system. however, the internal amplifier delay, pass transistors input capacitance, and the stray capacitance at the feedback node create additional poles in the system, and the output capaci- tors esr generates a zero. for proper operation, use the following equations to verify the linear regulator is properly compensated: 1) first, determine the dominant pole set by the linear regulators output capacitor and the load resistor: the unity-gain crossover of the linear regulator is: f crossover = a v_lr x f pole_lr 2) the pole created by the internal amplifier delay is approximately 1mhz: f pole_amp = 1mhz 3) next, calculate the pole set by the transistors input capacitance, the transistors input resistance, andthe base-to-emitter pullup resistor: g m is the transconductance of the pass transistor and f t is the transition frequency. both parameters can be foundin the transistors data sheet. because r be is much greater than r in , the above equation can be simplified: f= 1 2cr pole_in in in f= 1 2c pole_in i n nb ei n (r //r ) where: c= g 2f r= h g in m t in fe m , f= i 2c v pole_lr load(max)_lr out_lr out_lr r= v 0.1ma = 0.7v 0.1ma =6.8k be be ? a( 10 v )( i i )] v v_lr t bias load_lr ref ?+ [1 h ef p=i (v -v ) load(max)_lr in(max)_lr out_lr i= ( i - v r )h load(max) drv be be fe(min) internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 28 ______________________________________________________________________________________ downloaded from: http:///
substituting for c in and r in yields: 4) next, calculate the pole set by the linear regulators feedback resistance and the capacitance betweenfb_ and agnd (including stray capacitance): where c fb is the capacitance between fb_ and agnd, r upper is the upper resistor of the linear regulators feedback divider, and r lower is the lower resistor of the divider. 5) next, calculate the zero caused by the output capacitors esr: where r esr is the equivalent series resistance of c out_lr . to ensure stability, choose c out_lr large enough so the crossover occurs well before the polesand zero calculated in steps 2 to 5. the poles in steps 3 and 4 generally occur at several megahertz, and using ceramic capacitors ensures the esr zero occurs at several megahertz as well. placing the crossover below 500khz is sufficient to avoid the amplifier-delay pole and generally works well, unless unusual compo- nent choices or extra capacitances move one of the other poles or the zero below 1mhz. applications information power dissipation an ics maximum power dissipation depends on thethermal resistance from the die to the ambient environ- ment and the ambient temperature. the thermal resis- tance depends on the ic package, pcb copper area, other thermal mass, and airflow. more pcb copper, cooler ambient air, and more airflow increase the possi- ble dissipation, while less copper or warmer air decreases the ics dissipation capability. the major components of power dissipation are the power dissi- pated in the step-up regulator and the power dissipat- ed by the operational amplifiers. step-up regulator the largest portions of power dissipation in the step-upregulator are the internal mosfet, the inductor, and the output diode. if the step-up regulator has 90% effi-ciency, approximately 3% to 5% of the power is lost in the internal mosfet, approximately 3% to 4% in the inductor, and approximately 1% in the output diode. the remaining 1% to 3% is distributed among the input and output capacitors and the pcb traces. if the input power is about 5w, the power lost in the internal mosfet is approximately 150mw to 250mw. use the following for- mula to estimate the power loss on the built-in power mosfet: where r dson is the on-resistance for the power mosfet. the switching losses have not been account-ed for in this calculation. level-shifting scan driver the power dissipation in the ic per level-shifter outputdepends on the level-shifter operating frequency (f ls ), the voltage differential between v ghon and v goff , and the level-shifter output resistance.the power for each dissipation each channel can be calculated by: where r panel and c panel are the equivalent resis- tance and capacitance of the panel, r d1 and r d2 are the output resistance of the scan drivers.since two channels (sth1, sth2) are used as the start- pulse signal, the operating frequency is much lower compared to other channels. the power dissipation for both channels can be ignored. operational amplifiers the power dissipated in the operational amplifier (includ-ing programmable vcom calibrator) depends on the out- put current, the output voltage, and the supply voltage: where i out_source is the output current sourced by the operational amplifier and i out_sink is the output current that the operational amplifier sinks. pd = i v - v pd source out_source sup out sink () = =i v out_sink out p= c( v- v)f 2 ( r r lso panel ghon goff 2 ls d1 panel + +r + r r+ r ) d1 d2 panel d2 p( i lx_on in(dc,max) dr dson ) 2 f= 1 2c r pole_esr out_lr esr f= 1 2 c (r //r ) pole_fb fb upper lower f= f h pole_in t fe max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 29 downloaded from: http:///
max17100 vcom calibrator interface the max17100 is a slave-only device with a serialaddress of 9eh. the 2-wire serial interface (pins scl and sda) is designed to attach to a 1.8v to 4v serial bus. connect both scl and sda lines to the v in supply through individual pullup resistors. calculate therequired value of the pullup resistors using: where t r is the rise time in the electrical characteristics and c bus is the total capacitance on the bus. the max17100 uses a nonstandard serial interface pro-tocol with mostly standard voltage and timing parame- ters, as defined in the following subsections. bus free both data and clock lines remain high. data transferscan be initiated only when the bus is not busy (figure 13). start condition (s) starting from an idle bus state (both sda and scl arehigh), a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition from a master device on the bus. stop condition (p) a low to high transition of the sda line while theclock (scl) is high determines a stop condition. all operations must be ended with a stop condition from the master device. data valid the state of the data line represents valid data when,after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low peri- od of the clock signal. the master generates one clock pulse per bit of data during write operations and the slave device outputs 1 data bit per clock pulse during read operations. each data transfer is initiated with a start condition and terminated with a stop condition. two bytes are transferred between the start and stop conditions. slave address after generating a start condition, the bus mastertransmits the slave address consisting of the 7-bit device code (b1001111 or 9eh) for the max17100 (figure 14). for a read operation, the 8th bit is 1 and for write operations it is 0. the max17100 continuously monitors the bus for its corresponding slave address. it generates an acknowledge bit if it recognizes its slave address and it is not busy programming the mtp. r t c pullup r bus internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 30 ______________________________________________________________________________________ figure 13. serial bus start, stop, and data change conditions scl sda start condition s stop condition p data line stable data valid change of data allowed figure 14. serial slave address and data byte read byte: w = 0, max17100 outputs d6?0 followed by prog = 0 write byte: w = 1, data = d6?0, prog = 1 program mtp: w = 1, d6?0 = don't care, prog = 0 data byte slave address 1001111 s t ar t s t o p ac k a c k w pr og d6 d0 d1 d2 d3 d4 d5 downloaded from: http:///
data byte the data byte follows successful transmission of themax17100s slave address (figure 14). for a read operation, the max17100 will output the 7 bits corre- sponding to the current dac setting followed by a 0 bit. for a write operation, the bus master must provide the 7-bit data corresponding to the desired dac setting fol- lowed by a 1 bit. to program the ics mtp, the master must make the last bit a zero, in which case the other 7 bits of data are ignored. for programming, sup must exceed its programming threshold (8v min). otherwise, programming will not occur and the max17100 will not acknowledge the programming command. dac values table 3 lists the dac values and the correspondingi rset , v rset and v vcom values. acknowledge/polling the max17100, when addressed, generates an acknowl-edge pulse after the reception of each byte (figure 15). the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse so that the sda line is sta- ble low during the high period of the acknowledge- related clock pulse. of course, setup and hold times must be taken into account. the master signals an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave leaves the data line high to enable the master to generate the stop condition. the max17100 does not generate an acknowledge while an internal programming cycle is in progress. once the internally timed write cycle has started and the mtp inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address byte. only if the internal write cycle has completed does the max17100 respond with an acknowledge pulse, allowing the read or write sequence to continue. the max17100 does not acknowledge a command to program the mtp if sup is not high enough to properly program the device. also, a program command must be preceded by a write command. the ic does not acknowledge a program command or program the mtp unless the dac data has been modified since the most recent program command. max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 31 figure 15. serial bus acknowledge scl from master data output by max17100 data output by master clk1 start condition s 1 clk2 2 clk8 8 clk9 9 acknowledge clock pulse acknowledge not acknowledge d7 d6 d0 table 3. dac settings 7-bit data byte i rset v rset (v) v vcom (v) 0000000 i rset(min) v rset ( min ) v max 0000001 i rset(min) + 1 lsb v rset(min) + 1 lsb v max - 1 lsb .. . .. . .. . .. . 1111110 i rset(max) - 1 lsb v rset(max) - 1 lsb v min + 1 lsb 1111111 i rset ( max ) v rset ( max ) v min downloaded from: http:///
max17100 pcb layout and grounding careful pcb layout is important for proper operation.use the following guidelines for good pcb layout: ? minimize the area of high-current loops by placing the inductor, the output diode, and the output capaci-tors near the input capacitors and near the lx and pgnd pins. the high-current input loop goes from the positive terminal of the input capacitor to the inductor, to the ics lx pin, out of pgnd, and to the input capacitors negative terminal. the high-current output loop is from the positive terminal of the input capacitor to the inductor, to the output diode (d1), and to the positive terminal of the output capacitors, reconnecting between the output capacitor and input capacitor ground terminals. connect these loop com- ponents with short, wide connections. avoid using vias in the high-current paths. if vias are unavoidable, use many vias in parallel to reduce resistance and inductance. create a power-ground island (pgnd) consisting of the input and output capacitor grounds, pgnd pin, and any charge-pump components. connect all of these together with short, wide traces or a small ground plane. maximizing the width of the power ground traces improves efficiency and reduces output voltage ripple and noise spikes. create an analog ground plane (agnd) consisting of the agnd pin, all the feedback-divider ground con- nections, the operational-amplifier divider ground connections, the comp and tgs capacitor groundconnections, and the devices exposed backside pad. connect the agnd and pgnd islands by con- necting the pgnd pin directly to the exposed back- side pad. make no other connections between these separate ground planes. ? place all feedback voltage-divider resistors within 5mm of their respective feedback pins. the dividerscenter trace should be kept short. placing the resis- tors far away causes their fb traces to become antennas that can pick up switching noise. take care to avoid running any feedback trace near lx or the switching nodes in the charge pumps, or provide a ground shield. ? place the in pin and ref pin bypass capacitors as close to the device as possible. the ground connec-tion of the in bypass capacitor should be connected directly to the agnd pin with a wide trace. ? minimize the length and maximize the width of the traces between the output capacitors and the load forbest transient responses. ? minimize the size of the lx node while keeping it wide and short. keep the lx node away from feed-back nodes (fb, fbp, and fbn) and analog ground. use dc traces to shield if necessary. refer to the max17100 evaluation kit for an example ofproper pcb layout. internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 32 ______________________________________________________________________________________ downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds ______________________________________________________________________________________ 33 serial interface v cn v cp gate step-up controller in comp switch control 1 v in max17100 ghc1 ghd1 ghd2 ghon v cp v ghon v goff tgs scl 7 7 yv1c1 yv1c2 ghc2 sda mtp dac wrdrvp fbp st1 ghon ghc1 ghc2 st2 ck1 ckb1 ck2 ckb2 goff sth1 sth2 ckh1 ckbh1 ckh2 ckbh2 lx fb pgnd agnd sup out1 v main pos1 rset drvn fbn v cn v goff ref rst gate-on controller gate-off controller thermal shutdown switch control 2 ref voltage detector out2 pos2 out3 pos3 comfb ognd vcom comadj ep minimal operating circuit downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds 34 ______________________________________________________________________________________ package type package code outline no. land pattern no. 48 tqfn t4866+1 21-0141 90-0056 chip information process: bicmos top view thin qfn 13 14 15 16 17 18 19 20 21 22 23 24 ckbh2 ckh2 sth2 ckbh1 ckh1 sth1 yv1c1 ckb2 ck2 ckb1 ck1 st2 48 47 46 45 *ep 44 43 42 41 40 39 38 37 1 2 + 34 5 678910 11 12 fb rst pgnd lx gate in agnd sda scl wr rset comadj goff ghd2 ghd1 ghon tgs drvp fbp agnd ref fbn drvn comp 36 35 34 33 32 31 30 29 28 27 26 25 st1 yv1c2 pos3 out3 pos2 out2 pos1 out1 vcom comfb sup ognd max17100 pin configuration package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package draw-ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. downloaded from: http:///
max17100 internal-switch boost regulator with integrated scan driver, vcom calibrator, and op amp for tft lcds maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 35 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 5/9 initial release 1 8/10 reduced test time 2, 3, 4, 6C10, 15, 21, 34, 35 downloaded from: http:///

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